ARM, RISC-V контроллеры

Ну таймер всетаки более узко заточен , но и для него думаю можно накропать нечто подобное ) 

в планировщике оформлено вот так

//  пул используемых таймеров 

static const sch_timers_pool_t  sch_timers_pool[SCH_TIMERS_SIZE] = 

{

    { SCH_TIMER1, SCH_TIMER1_RCC, SCH_TIMER1_IRQ},

    { SCH_TIMER2, SCH_TIMER2_RCC, SCH_TIMER2_IRQ},

    { SCH_TIMER3, SCH_TIMER3_RCC, SCH_TIMER3_IRQ},

};

static const sch_task_pool_t    sch_task_pool[SCHEDULER_TAB_SIZE] = 

{

    { SCH_TIMER1, &SCH_TIMER1->CNT,  &SCH_TIMER1->CCR1},

    { SCH_TIMER1, &SCH_TIMER1->CNT,  &SCH_TIMER1->CCR2},

    { SCH_TIMER1, &SCH_TIMER1->CNT,  &SCH_TIMER1->CCR3},

    { SCH_TIMER1, &SCH_TIMER1->CNT,  &SCH_TIMER1->CCR4},

    { SCH_TIMER2, &SCH_TIMER2->CNT,  &SCH_TIMER1->CCR1},

    { SCH_TIMER2, &SCH_TIMER2->CNT,  &SCH_TIMER1->CCR2},

    { SCH_TIMER2, &SCH_TIMER2->CNT,  &SCH_TIMER1->CCR3},

    { SCH_TIMER2, &SCH_TIMER2->CNT,  &SCH_TIMER1->CCR4},

    { SCH_TIMER3, &SCH_TIMER3->CNT,  &SCH_TIMER1->CCR1},

    { SCH_TIMER3, &SCH_TIMER3->CNT,  &SCH_TIMER1->CCR2},

    { SCH_TIMER3, &SCH_TIMER3->CNT,  &SCH_TIMER1->CCR3},

    { SCH_TIMER3, &SCH_TIMER3->CNT,  &SCH_TIMER1->CCR4},

};

//  хранилище планировщика 

static task_t scheduler_tab[SCHEDULER_TAB_SIZE] = { 0 };