ARM, RISC-V контроллеры

Этот код работает.. To: lamerok This code works. Compiler: GCC 3.2 (CrossWorks v.1.2) //------------------------------------------------------------- // UART0 init - FIFO enabled,IRQ enabled(later) //------------------------------------------------------------- void InitUART0(void) { //---- pinout ----- rPCB_PINSEL0 = (rPCB_PINSEL0 & ~0xF) | ( 1 | (1<<2)); //-- enable access to divisor latch regs rUART0_LCR = LCR_ENABLE_LATCH_ACCESS; //-- set divisor for desired baud rUART0_DLM = 0; rUART0_DLL = 32; // (14.746*4)/16*115200 = 32 //-- disable access to divisor latch regs (enable access //-- to xmit/rcv fifos //-- and int enable regs) rUART0_LCR = LCR_DISABLE_LATCH_ACCESS; //-- Enable UART0 interrupts rUART0_IER = 3; //-- Enable RDA(Receive Data Available) int //-- Int Trigger - 4 bytes, Enable FIFO,Reset //-- Tx FIFO & Rx FIFO rUART0_FCR = (0x3<<6) | 1; //-- setup line control reg - disable break transmittion, //-- even parity, 1 stop bit, 8 bit chars rUART0_LCR = 0x13;//-- 0b00010011 } //============================================================= //========================= Interrupts ======================== //============================================================= I not use VIC registers from LPC21XX; /*----------------------------------------------------------- * IRQ HANDLER * * Description: This handles all the IRQs *-----------------------------------------------------------*/ OS_CPU_IRQ_ISR: STMFD SP!,{R0-R3,R12,LR} BL OSIntEnter /* Indicate beginning of ISR */ BL OS_CPU_IRQ_Handler /* Handle interrupt */ BL OSIntExit /* Indicate end of ISR */ LDR R0,L__OS_IntCtxSwFlag /* See if we need to do a context switch */ LDR R1,[R0] CMP R1,#1 BEQ OS_IntCtxSw /* Yes, Switch to Higher Priority Task */ LDMFD SP!,{R0-R3,R12,LR} /* No, Restore registers of interrupted task's stack */ SUBS PC,LR,#4 /* Return from IRQ */ //------------------------------------------------------- // IRQ Handler //------------------------------------------------------- void OS_CPU_IRQ_Handler (void) { register int irq_stat; INT8U err; irq_stat = VICIRQStatus; //----- Timebase 1 ms int ---------- if((irq_stat & (1<<8)) > 0) //-- Source - PWM unit { //---- Clear Int source ------- rPWM0_IR = 0x0000070F; //-- 111 0000 1111 //------- Do some processing here -------- //-------------------------------------------- //-- !!! You need check and read UART TX FIFO,otherwise //-- !!! you never get UART TX FIFO int if((rUART0_LSR & (1<<5))>0) { data = (int)OSQAccept(queueTxUart0,&err); if(err == OS_NO_ERR) //-- get sym from queue { rUART0_THR = data; } } OSTimeTick(); // interrupt 1ms is the tick source, // so call OSTimeTick() } //---- UART 0 rx int else if((irq_stat & (1<<6)) > 0) //-- Source - UART0 { //--- Reset Int Req i = rUART0_IIR; // interrupt id-RO //--- UART FIFO TX empty check if((rUART0_LSR & (1<<5))>0) { for(i=0;i<12(or 16);i++) //-- UART TX FIFO depth ->16 //-- in fact, I use 12,not 16 { data = (int)OSQAccept(queueTxUart0,&err); if(err == OS_NO_ERR) //-- get sym from queue { rUART0_THR = data; } else break; } } //--- UART FIFO RX trigger level check while((rUART0_LSR & 0x01) > 0) //-- while Rx FIFO is not empty { data = rUART0_RBR; OSQPost(queueRxUart0,(void*)data); } } //---- Int 0 int else if((irq_stat & (1<<14)) > 0) //-- Source - INT0 { //------- Do some processing here -------- //-------------------------------------------- } }