Программируемая логика и ЦОС

library ieee;
use ieee.std_logic_1164.all;

ENTITY NK_test IS
PORT(
	inS1 : in std_logic;
	inS2, inS3 : in std_logic;
	outS4 : out std_logic
);
END ENTITY;

ARCHITECTURE RTL OF NK_test IS
	signal r_S4 : std_logic;
	signal r_oS1 :std_logic;
	signal w_X1 : std_logic;
	signal w_X2 : std_logic;
BEGIN
	w_X1 <= not inS2 or inS3;
	w_X2 <= inS2 or inS3;
	
	
	process(w_X1)
	begin
		if (rising_edge(w_X1)) then 
			r_oS1 <= inS1;
		end if;
	end process;
	
	process(w_X2)
	begin
		if (rising_edge(w_X2)) then 
			r_S4 <= r_oS1;
		end if;
	end process;
	
	outS4 <= r_S4;
	
END RTL;