Nikolay_Po (21.10.2017 12:51) , в ответ на – 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines. автор: _basile
Спасибо. Оказалось, я по неграмотности искал "bootloader", а надо было "boot loader". Спасибо за наводку. Вот что я написал напарнику, который так же не работал с подобными чипами:
The SAM4S chip has an ERASE input, look at page 14, table 3-1 of 11100K datasheet. This pin is present on 48-pin chip version, see page 26, table 4-7.
The description of an ERASE pin directly says the chip may be programmed without a debug tool. ROM boot loader can be started by this pin:
"6.5 ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as logic level 1). The ERASE pin and the ROM code ensure an in-situ reprogrammability of the Flash content without the use of a debug tool. When the security bit is activated, the ERASE pin provides the capability to reprogram the Flash content. It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in Table 44-74 “AC Flash Characteristics”.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted erasing. Refer to Section 11.2 “Peripheral Signal Multiplexing on I/O Lines” on page 51. Also, if the ERASE pin is used as a standard I/O output, asserting the pin to low does not erase the Flash".
Here is ERASE state entrance procedure:
"The following sequence ensures the erase operation in all cases:
1. Assert the ERASE pin (High)
2. Assert the NRST pin (Low)
3. Power cycle the device
4. Maintain the ERASE pin high for at least the minimum assertion time".
Here is a description how the ERASE will activate the ROM boot loader:
"8.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed using GPNVM bits.
A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
Setting GPNVM1 selects the boot from the Flash. Clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM1 and thus selects the boot from the ROM by default".
I think we should look for SAM-BA Boot
"126.96.36.199 SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0".