Средства и методы разработки

Сегодня наткнулся, позволю себе процитировать: https://en.wikipedia.org/wiki/Mill_architecture#The_belt,_a_pipelining_register_system

Ivan Godard, the designer of Mill, quotes research finding that during operation of a standard register machine, of values stored to processor registers: 6% are accessed never; 80%, once; and only 14%, more than once. Thus, the Mill uses a novel temporal register addressing scheme, the belt by analogy to a conveyor belt. The operands of the arithmetic logic units (ALUs) and other functional units may be taken from any position on the belt, and the result from the computation is dropped (stored) in the front position of the belt, advancing the belt to make room. As the belt is fixed length, drops in the front are matched by older operands falling off the back; pushed-off operands become inaccessible and must be explicitly saved if still needed for later work. Most operations of the instruction set work only with data on the belt, not on data registers or main memory cells. For a typical instruction like add, both argument operands come from explicitly named positions on the belt, and the result is dropped on the front, ready for the next instruction. Operations with multiple results simply drop more values at the belt front. Most belt instructions are encoded as just an operation code (opcode) and two belt positions, with no added fields to specify a result register, memory address, or literal constant. Constant operands are dropped by separate load immediate instructions. All access of program variables in main random-access memory (RAM) is segregated into separate load or store instructions containing one memory address, or some way to calculate that address from belt operands. It is hard for human programmers to keep track of belt contents, and hence operand addresses, when writing assembly code for a belt machine. However, it is easy for a compiler to track the changing contents and emit the correct position addresses in generated code. The belt is fixed length and may be too short to hold all live transient operands before they are pushed off the end. If an operand is needed for longer than its belt lifetime, it must be saved while still on the belt (spill) and later restored to the belt when needed again (fill). This situation is equivalent to the need to spill registers to memory when a program runs out of registers in a general-register machine. Spilled operands may be written to memory using normal store instructions, and restored using normal load instructions, or spill and fill may use special-purpose storage and associated operations that are faster or offer other advantages over load and store. The operands on the belt are read-only. New results do not overwrite prior values. The belt is thus a single-assignment structure, and is immune to the data hazards that must be dealt with by modern out-of-order general-register machines.

Рекомендую к чтению всю статью по ссылке. И пойти по ссылкам из статьи. Там интересного много, например: https://web.archiv …heMillArchitecture.pdf "34 to 300+ RISC-equivalent 32-bit operations per cycle per thread"

A patent US 9513921 on the belt was granted in 2016.

Всё, закопали. В этой жизни увидеть не прийдётся, вся надежда только на северокорейских диктаторов, решившихся наплевать и растоптать американское патентнтное право.