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Evgeny_CD, Архитектор (13.02.2020 17:46, просмотров: 97) в ответ на Изучаем ситуацию с наличием аппаратного деления. -> - автор: Evgeny_CD
PIC32 PIC32MM0256GPM064 - мелкие, недорогие и весьма качественные PIC32. 32 битное деление 11-33 такта Из описания ядра. MIPS32 microAptiv and M-Class Cores Divide operations are implemented with a simple 1 bit per clock iterative algorithm and require 35 clock cycles in the worst case to complete. The MDU is a separate pipeline for integer multiply and divide operations and DSP ASE multiply instructions (see Note). This pipeline operates in parallel with the integer unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows the long-running MDU operations to be partially masked by system stalls and/or other integer unit instructions. The MDU supports execution of one 32 x 32 multiply or multiply-accumulate operation every clock cycle. The 32-bit divide operation executes in 12-38 clock cycles. The MDU also implements various shift instructions operating on the HI/LO register and multiply instructions as defined in the DSP ASE. Но DSP ASE в этом чипе вроде бы нет. Из ДШ на чип •Multiply/Divide Unit (MDU): -Configurable using high-performance multiplier array. -Maximum issue rate of one 32x16 multiply per clock. -Maximum issue rate of one 32x32 multiply every other clock. -Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension dependent).
Прикреплённые файлы:
60001192B.pdfPIC32MM0256GPM064- …ly-Data-Sheet-DS60.pdf