Программируемая логика и ЦОС

module box(ins1, ins2, ins3, outs4);
	input ins1;
	input ins2;
	input ins3;
	output outs4;

	wire #1 ins1_n = ~ ins1;
	wire #1 ins1_edge = ~ (ins1 ^ ins1_n);

	wire #1 clk= ins2 | ins1_edge & ins3;
	wire d = ins1;
	reg q;

	always @(posedge clk)
		q<=d;
  
	assign outs4=q;
	 
endmodule

module main;  //module definition - no inputs or outputs
  
	reg ins1=0;
	reg ins2=0;
	reg ins3=0;
	wire outs4;

	box BOX(.ins1(ins1), .ins2(ins2), .ins3(ins3), .outs4(outs4));


	initial begin
		#10 ins1=1;
		#10 ins2=1;
		#10 ins2=0;
		#10 ins1=0;
		#10 ins2=1;
		#10 ins2=0;
		#10 ins1=1;
		#10 ins3=1;
		#10 ins1=0;
		#10 ins1=1;
		#10 ins2=1;
		#10 ins2=0;
		#10 ins3=0;
		#10 ins1=0;
		#10 ins1=1;
		#10 ins2=1;
		#10 ins2=0;
	end

	initial            //can have multiple initial blocks.
		$monitor ("Time = %d ins1 =%d ins2 =%d ins3 =%d outs4 = %d ",$time, ins1, ins2, ins3, outs4);

	initial
		#200 $finish;     //finish after 20 time units
	
endmodule