Программируемая логика и ЦОС

module Pause50
(
	input  wire wStart,
	input  wire clock_1MHz,
	output wire wPause50
);
reg [5:0] rPauseCounter50;
	always @( posedge clock_1MHz or posedge wStart )
		if( wStart )
			rPauseCounter50 <=  6'd50;
		else 
			if( |rPauseCounter50 )			// Пока счетчик не 0
				rPauseCounter50 <= rPauseCounter50 - 1'b1;
	assign wPause50 = ( rPauseCounter50 != 6'b0 );
endmodule