Программируемая логика и ЦОС

// выделяем фронт cpu_clk
// cpu_clk - вход
// cpu_clk_s - строб
  reg	[1:0]	cpu_clk_edge_det;
  reg		cpu_clk_s;
  always @(posedge sd_clk or negedge reset_n)
  begin
	if (reset_n == 0)
	begin
		cpu_clk_edge_det <= 0;
		cpu_clk_s <= 0;
	end
	else 
	begin
		cpu_clk_edge_det <= {cpu_clk_edge_det[0], cpu_clk};
		cpu_clk_s <= (cpu_clk_edge_det==2'b01);
	end
  end