Программируемая логика и ЦОС

library ieee;
use ieee.std_logic_1164.all;

ENTITY w_test IS
PORT(
	inS1 : std_logic;
	inS2, inS3 : std_logic;
	outS4 : out std_logic
);
END ENTITY;

ARCHITECTURE slt OF w_test IS
BEGIN
	process(inS1, inS2, inS3)
	begin
		if ( inS3 = '1') then
			outS4 <= inS1;
		elsif ( inS2'event and inS2='1') then -- rising_edge(inS2)
			outS4 <= inS1;
		end if;
	end process;
END; 

module V_test(inS1, inS2, inS3, outS4);
	// Input Port(s)
	input wire inS1;
	input wire inS2;
	input wire inS3;
	// Output Port(s)
	output reg [0:0] outS4;

	always @ (posedge inS3 or posedge inS2)
	begin
		if (inS3)
		begin
			outS4 <= inS1;
		end
		else
		begin
			outS4 <= inS1;
		end
	end
endmodule